Compact code generation for embedded applications on digital signal processors

Digital Signal Processors (DSPs) are a family of embedded processors with tight constraints on memory, area, and cost. Many such systems have irregular addressing modes where base-plus-offset mode is not supported. However, they have address generation units (AGUs) that can perform auto-increment/decrement address arithmetic instructions in parallel with the same Load/Store instruction. This can be utilized to reduce the number of explicit address arithmetic instructions to minimize the code size. An effective technique for optimized code generation is offset assignment. This technique reduces the code size by finding an offset assignment that can maximally utilize auto-increment/decrement. In this paper, we present an optimal integer linear programming (ILP) solution to the offset assignment problem with variable coalescing and variable permutation. Experimental results on several benchmarks show the effectiveness of our techniques.