Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization

This paper reports the optimization of area and power for a 32-point radix-2 hybrid FFT (Fast Fourier Transform). The strategy consists of using the Constant Matrix Multiplication (CMM) method along the stages of the 8-point FFT architecture, which is implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the butterflies. The 32-point FFT is obtained through the composition of the optimized 8-point FFT modules. The partial decomposition of coefficients allows the computation of all coefficients necessary for the 32-point through a control unit. We have compared our proposed architecture to an implemented behavioral, unrestricted architecture synthesized using the CADENCE Encounter RTL Compiler for the UMC130nm technology. The results show reductions up to 31% in area and 15% in power when using our proposed solution.