A Gated-Oscillator based Burst-Mode Clock and Data Recovery (CDR) Circuit

Author

Yan, Dan Lei ; Raja, M. Kumarasamy ; Ajjikuttira, Aruna B.

Author_Institution

Inst. of Microelectron., Singapore

fYear

2007

fDate

9-11 Dec. 2007

Firstpage

90

Lastpage

93

Abstract

This paper describes the detailed design considerations and verification of a 2.35-Gbps burst-mode clock and data recovery circuit. This CDR circuit utilizes a gated-oscillator clock recovery technique with an additional phase locked frequency acquisition circuit which enables it to lock to incoming random data within one or two bits. The CDR circuit was fabricated in 0.18 mum CMOS technology. The active chip area is 0.8times0.8 mm² and it consumes a total power of 130 mW from a single 1.8 V supply.

Keywords

CMOS digital integrated circuits; clocks; oscillators; synchronisation; CDR circuit; CMOS; bit rate 2.35 Gbit/s; burst-mode clock and data recovery circuit; gated-oscillator based circuit; phase locked frequency acquisition circuit; power 130 mW; size 0.18 micron; voltage 1.8 V; CMOS technology; Circuits; Clocks; Frequency synchronization; Inverters; Optical network units; Optical noise; Passive optical networks; Phase locked loops; Voltage-controlled oscillators; 2.5Gbps; OLT; ONU; PON; burst-mode; clock and data recovery;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology, 2007. RFIT 007. IEEE International Workshop on

Conference_Location

Rasa Sentosa Resort

Print_ISBN

978-1-4244-1307-2

Electronic_ISBN

978-1-4244-1308-9

Type

conf

DOI

10.1109/RFIT.2007.4443928

Filename

4443928