All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS

In this paper, we present an all-digital Power Amplifier (PA) that is fully integrated on chip using 0.18 μm CMOS process. This PA consists of 8 output-connected all-digital inverters controlled by an 8-phase clock generated using a multistage Phase Interpolator (PI). Experimentally, our architecture showed power consumption less than 0.03 mW/MHz, and tuning range from 400 to 900 MHz. This architecture will be used with our wireless transceiver that applies a modified BPSK as modulation.