Title :
A switched interconnection infrastructure to tightly-couple a RISC processor core with a coarse grain reconfigurable array
Author :
Garzia, Fabio ; Ahonen, Tapani ; Nurmi, Jari
Author_Institution :
Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland
Abstract :
This paper describes a novel interconnection infrastructure for a general purpose system composed of a RISC processor core and a coarse grain run time reconfigurable array. The proposed infrastructure is based on a nonblocking network of switches and provides a point to point connection between the two processing blocks and all the system peripherals. Modifications to the switches and adoption of separated clock domains allowed the achievement of a 3x speed-up in comparison with a bus based interconnection.
Keywords :
computer networks; reconfigurable architectures; reduced instruction set computing; system buses; RISC processor core; bus based interconnection; coarse grain reconfigurable array; point to point connection; switched interconnection infrastructure; Bandwidth; Clocks; Control systems; Coprocessors; Dairy products; Hardware; Reconfigurable architectures; Reduced instruction set computing; Runtime; Switches;
Conference_Titel :
Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.
Conference_Location :
Cork
Print_ISBN :
978-1-4244-3733-7
Electronic_ISBN :
978-1-4244-3734-4
DOI :
10.1109/RME.2009.5201372