Redefining CMOS logic style for subthreshold operation

Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65 nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65 nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.