Stress Characterization for Stress-Induced Voiding in Cu/Low K Interconnects with Geometry and Upper Cap Layer Dependences

We have conducted stress-induced voiding (SIV) experiments on Cu/low-k interconnect with different geometries of via structures and upper metal cap layers to evaluate their reliability impact. We showed the cap layer of upper metal had strong effect on the SIV performance. The degrees of such SIV degradations varied with different via structure geometries. A 3D Finite Element Analysis (FEA) is applied to simulate the stress fields inside these different via test structures with different upper cap layers. Different stress fields and gradient were found inside these different via schemes. We explained the different SIV performance of these via schemes with the stress results. TEM failure analysis was performed to locate the void location and to confirm the FEA stress results.