Effect of Threshold-Voltage Instability on SiC DMOSFET Reliability

Author

Lelis, A.J. ; Green, R. ; Habersat, D. ; Goldsman, N.

Author_Institution

Army Res. Lab., Adelphi, MD

fYear

2008

fDate

12-16 Oct. 2008

Firstpage

72

Lastpage

76

Abstract

The instability of the threshold voltage in SiC power DMOSFETs due to gate-bias stress and ON-state stress is a potential reliability issue, although the effects can be mitigated if the threshold voltage is set with enough positive margin so that no increase in OFF-state leakage occurs. In this case, the primary effect will be to increase the ON-state resistance by about five percent, which should be tolerable for power converter applications. Subthreshold-slope analysis of slower parameter-analyzer results reveal similar instabilities to those of fast I-V measurements.

Keywords

power MOSFET; power convertors; semiconductor device reliability; silicon compounds; stress effects; wide band gap semiconductors; OFF-state leakage; ON-state stress; SiC; fast I-V measurements; gate-bias stress; power DMOSFET reliability; power converter applications; subthreshold-slope analysis; threshold-voltage instability; Current measurement; Educational institutions; Electrical resistance measurement; Laboratories; Power measurement; Silicon carbide; Stress measurement; Subthreshold current; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International

Conference_Location

S. Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

978-1-4244-2194-7

Electronic_ISBN

1930-8841

Type

conf

DOI

10.1109/IRWS.2008.4796090

Filename

4796090