Strategic placement of reliable routers for the optimization of dependable dynamic NoC

We present an optimization of reliable Network on Chip (NoC) suitable for dynamic reconfigurable systems based on FPGA. The originality of our approach resides on a strategic placement of routers incorporating elements of dependability in order to detect and correct the errors of the data packets. The solution is a factorization of these reliable routers encompassing routers without any error detection block. This ensures the global reliability of the network, and reduces the area overhead and the latency of the data packets. We present a theoretical study and hardware implementations which validates our reliable approach.