Quantitative reliability assessment of Plasma Induced Damage on product wafers with fast WLR measurements

This paper describes the assessment of a plasma induced damage (PID) event in the metal stack of an 8 inch 130 nm process line. The relevant PID stress and measurement sequence used, during standard productive fast wafer level reliability (fWLR) monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the PID effect. It is demonstrated that the complete investigation can be done on productive wafers in a very short time and only on scribe line test structures, saving time and and extra wafer cost.