DocumentCode
2922424
Title
Negative Bias Temperature Stress on PFETs within fast Wafer Level Reliability Monitoring
Author
Vollertsen, R.-P. ; Reisinger, H. ; Schlunder, Christian
Author_Institution
Infineon Technol. AG, Munich
fYear
2008
fDate
12-16 Oct. 2008
Firstpage
86
Lastpage
90
Abstract
The challenges of measuring by means of fast WLR the Vt degradation caused by temperature bias stress are discussed in this work. Two methods, the fast two point measurement with smart intermediate stress (SIS) and the back-extrapolation based on measuring the recovery curve are compared. Considering the properties of the test equipment an adjusted SIS approach is implemented in order to get an equivalent method to the stress interruption free OTF-method. Nevertheless recovery causes a stronger degradation vs. time dependence at short times than at long times leading to the implementation of the back-extrapolation of the recovery curve. This method requires the implementation of a curve fitting algorithm like the Levenberg-Marquardt algorithm in the fWLR stress routine for data evaluation upon completion of the stress. The method was tested on three PFET types with different oxide thickness and in all cases shows reasonable results for various stress conditions.
Keywords
field effect transistors; semiconductor device reliability; Levenberg-Marquardt algorithm; PFET; back-extrapolation; curve fitting algorithm; negative bias temperature stress; recovery curve; smart intermediate stress; temperature bias stress; wafer level reliability monitoring; Current measurement; Degradation; Monitoring; Niobium compounds; Stress measurement; Temperature; Testing; Thermal stresses; Thickness measurement; Titanium compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Reliability Workshop Final Report, 2008. IRW 2008. IEEE International
Conference_Location
S. Lake Tahoe, CA
ISSN
1930-8841
Print_ISBN
978-1-4244-2194-7
Electronic_ISBN
1930-8841
Type
conf
DOI
10.1109/IRWS.2008.4796093
Filename
4796093
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