A method to project hot carrier induced punch through voltage reduction for deep submicron LDD PMOS FETs at room and elevated temperatures

Author

Fang, Peng ; Yue, John T. ; Wollessen, Don

Author_Institution

Advanced Micro Devices, Sunnyvale, CA, USA

fYear

1992

fDate

March 31 1992-April 2 1992

Firstpage

131

Lastpage

135

Abstract

The hot-electron-induced punchthrough (HEIP) voltage (V/sub pt/) characterization technique, which can be used for half- and sub-half-micron lightly doped drain (LDD) PMOS reliability characterization, was established. It was found that, unlike other hot carrier effects, the punchthrough due to HEIP at room temperature or the temperature effects plus HEIP at higher temperatures is the most significant limitation for deep submicron LDD PMOSFETs. The high-temperature effects of V/sub pt/ were also quantified at 25 degrees C, 80 degrees C and 125 degrees C ambient temperatures. The oxide quality dependence of the HEIP was also studied.<>

Keywords

hot carriers; insulated gate field effect transistors; reliability; 25 to 125 C; HEIP; PMOSFETs; characterization technique; deep submicron LDD PMOS FETs; elevated temperatures; high-temperature effects; hot carrier effects; hot-electron-induced punchthrough; lightly doped drain; oxide quality dependence; punch through voltage reduction; reliability characterization; reliability performance limit; room temperature; sub half micron PMOSFET; Avalanche breakdown; CMOS technology; Current limiters; Degradation; Hot carrier effects; Hot carriers; MOSFET circuits; Secondary generated hot electron injection; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium 1992. 30th Annual Proceedings., International

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-0473-X

Type

conf

DOI

10.1109/RELPHY.1992.187637

Filename

187637