High-level design and synthesis of a resource scheduler

Given the increasing complexity of current embedded systems, hardware design is being pushed to a higher level of abstraction, with High-Level Synthesis tools enabling hardware synthesis from untimed C++. Still, HLS technology does not provide a clear methodology to derive both hardware and software implementations from a single high-level code. This paper describes the design, implementation and evaluation of a resource scheduler that has a single C++ description and is automatically implementable in both software and hardware.