Phase Noise and Power Optimization of a 2-GHz Differential CMOS LC VCO

The phase noise and power optimization of a 2-GHz differential LC VCO by CMOS 0.18-mum RF 1P6M technology is presented. The key ideas to achieve phase noise optimization are delicate designs of a symmetric circuit and a technology to filter out the top-biased transistor´s noise. Moreover, In order to obtain good phase noise performance with low power consumption, the oscillation output amplitudes are well designed to ensure the differential pair transistors operate at the boundary between saturation and triode. The phase noise is -102.6dBc/Hz at 100 kHz and -121.1dBc/Hz at 600 kHz offset frequencies with a 12.4% tuning range for a 3 mA biased current.