ILP formulation for hybrid FPGA MPSoCs optimizing performance, area and memory usage

In this paper an integer linear programming (ILP) model is proposed for identifying the optimal resources allocation and application partitioning on FPGA-based hybrid MPSoC, including the memory allocation for each processing unit and total BRAM usage on the device. The motivation behind this work is the reduction of the necessary exploration time for the identification of the optimal hybrid MPSoC architecture implementation for each particular application. Whilst many ILP model approaches have been proposed, none of the existing models presents an accurate calculation model for the BRAM usage on the FPGA device and can impose the memory usage and/or BRAM usage as a design constraint. Our work comes to fill this void, especially now that modern multimedia applications have an ever increasing need for memory space and data throughput.