Reliability Simulation and Design Consideration of High Speed ADC Circuits

For the first time, a high speed flash ADC is developed for reliability analysis and simulation of analogue and mix-signal circuit. All the three failure mechanisms (NBTI, HCI, TDDB) are quantified with degradation models. The result shows that pMOS degradation especially NBTI is the most detrimental failure mechanism for the normal operation of high speed ADC, which leads to the fault output. Based on the analysis of the reliability-critical parts, reliability improvement approaches are suggested for the reliable design.