DocumentCode :
292353
Title :
Fast acquisition PLL frequency synthesizer with improved N-stage cycle swallower
Author :
Saba, Takahiko ; Park, Duk-Kyu ; Mori, Shinsaku
Author_Institution :
Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
Volume :
1
fYear :
1993
fDate :
19-21 May 1993
Firstpage :
77
Abstract :
A new type of fast acquisition frequency synthesizer which improves the operation of the NSCS (N-stage cycle swallower) is proposed. By varying the output frequency of the NSCS and by adopting a programmable divider, the proposed synthesizer has an output frequency of deviation within 0.0003 ppm. By introducing an extra switching operation of the last stage division ratio in the NSCS, the proposed synthesizer can have an extremely fast acquisition time
Keywords :
digital phase locked loops; direct digital synthesis; frequency dividers; frequency response; N-stage cycle swallower; PLL frequency synthesizer; fast acquisition; programmable divider; Communication switching; Frequency conversion; Frequency synthesizers; Phase locked loops; Pulse generation; Telecommunication switching; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-0971-5
Type :
conf
DOI :
10.1109/PACRIM.1993.407216
Filename :
407216
Link To Document :
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