Random walk analyses of two discrete phase control digital bit synchronizers

Random walk models are used to analyze the performance of two digital bit synchronizers that use hard limiting of the received signal, and that allow the estimated timing phase to change by a fixed amount each symbol period. One of these uses a decision directed version of Gardner´s algorithm, while the other uses a technique called sample-correlate-choose-smallest (SCCS). For the first method, exact solutions for the RMS phase-jitter, mean time to acquire synchronization, and mean time to symbol slip in the case of binary non return-to-zero (NRZ) signaling are found. In contrast to previous solutions, these results do not increase in complexity as the phase step size decreases. For practical purposes, there is a negligible difference between the exact results and those obtained from an approximate model. This approximate model is used to evaluate the performance of the algorithm with shaped time limited pulses. Jitter, acquisition, and symbol slip performance are evaluated for the second algorithm using NRZ signals. It is found that SCCS performs significantly better at small SNR, while Gardner´s algorithm can have an advantage above approximately 0 dB