DocumentCode :
2924016
Title :
Design of a Compact Modular Exponentiation Accelerator for Modern FPGA Devices
Author :
Alho, Timo ; Hamalainen, P. ; Hännikäinen, Marko ; Hämäläinen, Timo D.
Author_Institution :
Tampere Univ. of Tech., Tampere
fYear :
2006
fDate :
24-26 July 2006
Firstpage :
1
Lastpage :
7
Abstract :
We present a compact FPGA implementation of a modular exponentiation accelerator suited for cryptographic applications. The implementation efficiently exploits the properties of modern FPGAs. The accelerator consumes 341 logic elements, 1 DSP block, and 13604 memory bits in Altera Stratix EP1S40. It performs modular exponentiations with up to 2250-bit integers and scales easily to larger exponentiations. Excluding pre and post processing time, 1024-bit and 2048-bit exponentiations are performed in 28.03 ms and 212.09 ms, respectively. Due to its compactness, standard interface, and support for different clock domains, the accelerator can effortlessly be integrated into a larger system in the same FPGA.
Keywords :
cryptography; digital signal processing chips; field programmable gate arrays; Altera Stratix EP1S40; DSP block; FPGA; clock domains; compact modular exponentiation accelerator; cryptographic applications; Application specific integrated circuits; Clocks; Cryptographic protocols; Cryptography; Design automation; Embedded system; Field programmable gate arrays; Hardware; Phase locked loops; Programmable logic arrays; FPGA; Modular exponentiation; Montgomery multiplication; compact; cryptography; hardware;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Automation Congress, 2006. WAC '06. World
Conference_Location :
Budapest
Print_ISBN :
1-889335-33-9
Type :
conf
DOI :
10.1109/WAC.2006.375738
Filename :
4259811
Link To Document :
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