Implementation of high performance and low leakage half subtractor circuit using AVL technique

In this paper, we propose a leakage reduction technique as high leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits. Sub threshold leakage current plays a very important role in power dissipation so to reduce the sub threshold leakage current we proposed an adaptive voltage level (AVL) technique. Which optimize the overall voltage across the half subtractor circuit in standby mode. In this AVL technique, two schemes are employed, one is AVLS (adaptive voltage level at supply) in which the supply voltage is reduced and the other is AVLG (adaptive voltage level at ground) in which the ground potential is increased. By applying this technique we have reduced the leakage current from 9.274*10-12ampere) to 5.428*10-12amp. That means this technique the leakage current 41.4%. The circuit is simulated on Cadence(R) Virtuoso(R) in 45nano meter CMOS technology. Simulation results reveal that there is a significant reduction in leakage current for this proposed cell with the AVL circuit reducing the supply voltage.