Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronics

Author

Goodson, K.E. ; Flik, M.I.

Author_Institution

Dept. of Mech. Eng., MIT, Cambridge, MA, USA

fYear

1992

fDate

5-8 Feb 1992

Firstpage

122

Lastpage

126

Abstract

It is pointed out that silicon-on-insulator (SOI) electronics have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the device power and the limit on the channel temperature. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, electrons in aluminum, and phonons in silicon. If microscale effects are not considered, the packing limit is overpredicted by 22% for a substrate temperature of 300 K and 100% for substrate temperature of 77 K

Keywords

MOS integrated circuits; cooling; insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; 300 K; 77 K; SOI MOSFET devices; channel temperature; device cooling; device operating temperature; device power; microscale effects; microscale thermal conduction; packing limit; substrate temperature; thermal packing limit; Aluminum; Electronics cooling; Electrons; MOSFET circuits; Power MOSFET; Scattering; Silicon compounds; Silicon on insulator technology; Temperature; Thermal conductivity;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal Phenomena in Electronic Systems, 1992. I-THERM III, InterSociety Conference on

Conference_Location

Austin, TX

Print_ISBN

0-7803-0503-5

Type

conf

DOI

10.1109/ITHERM.1992.187749

Filename

187749