DocumentCode :
2924398
Title :
A Cache Architecture for Counting Bloom Filters
Author :
Ahmadi, Mahmood ; Wong, Stephan
Author_Institution :
Delft Univ. of Technol., Delft
fYear :
2007
fDate :
19-21 Nov. 2007
Firstpage :
218
Lastpage :
223
Abstract :
Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., utilizing multi-level memory hierarchies, special hardware architectures, and hardware threading. In this paper, we introduce a multi-level memory hierarchy and a special hardware cache architecture for counting Bloom filters that is utilized by network processors and packet processing applications such as packet classification and distributed web caching systems. Based on the value of the counters in the counting Bloom filter, a multi-level cache architecture called the cache counting Bloom filter (CCBF) is presented and analyzed. The results show that the proposed cache architecture decreases the number of memory accesses by at least 51.3% when compared to a standard Bloom filter.
Keywords :
Internet; cache storage; memory architecture; counting bloom filters; distributed web caching systems; memory accesses; multilevel memory hierarchies; network processors; packet classification; packet processing systems; Aging; Computer architecture; Counting circuits; Delay; Hardware; Information filtering; Information filters; Laboratories; Mathematics; Performance analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networks, 2007. ICON 2007. 15th IEEE International Conference on
Conference_Location :
Adelaide, SA
ISSN :
1556-6463
Print_ISBN :
978-1-4244-1230-3
Electronic_ISBN :
1556-6463
Type :
conf
DOI :
10.1109/ICON.2007.4444089
Filename :
4444089
Link To Document :
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