An FPGA controlled WDM buffer memory

Summary form only given. Recent advance in dense wavelength division multiplexing (DWDM) technology has provided tremendous bandwidth on optical fiber communications. However, the capability of switching and routing information at this high bandwidth (e.g. 1 terabit/s) has been behind the transmission capability. Building a large capacity switching system using only electronic technology may potentially lead to a system bottleneck in interconnecting many electronic devices or modules, mainly caused by enormous interconnection wires and electromagnetic interference among them. We have explored the possibility of switching ATM cells in the optical domain by prototyping a WDM ATM Multicast (3M) switch. By taking the advantages of both optical and electronic technologies, we have constructed two planes, an optical switching plane and an electronic control plane. ATM cells are routed through the optical switching plane, while their headers are extracted and processed in the electronic plane that controls the optical devices and routes the cells to proper output port(s). We have implemented and demonstrated two subsystems, one that performs the cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s, another performs optical cell synchronization which aligns the phases of incoming optical ATM cells at 2.5 Gb/s to a reference cell clock with the adjustment ranges from 1 to 511 bits and a precision of 1/4 bit (100 ps), and an integrated 1/spl times/2 Y-junction semiconductor optical amplifier (SOA) switch is developed to facilitate the cell synchronizer.