Title :
A 1 GHz CMOS comparator with dynamic offset control technique
Author :
Zhu, Xiaolei ; Tsukamoto, Sanroku ; Kuroda, Tadahiro
Author_Institution :
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama
Abstract :
A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.
Keywords :
CMOS integrated circuits; charge compensation; comparators (circuits); CMOS comparator; charge compensation; dynamic offset control technique; frequency 1 GHz; power 380 muW; timing control; voltage 1.2 V; Absorption; CMOS technology; Capacitors; Circuits; Clocks; Delay; Latches; Preamplifiers; Timing; Voltage control;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796453
