DocumentCode
2924902
Title
A low-power FPGA based on autonomous fine-grain power-gating
Author
Ishihara, Shota ; Hariyama, Masanori ; Kameyama, Michitaka
Author_Institution
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai
fYear
2009
fDate
19-22 Jan. 2009
Firstpage
119
Lastpage
120
Abstract
This is the first implementation of an FPGA based on autonomous fine-grain power-gating. To cut the power consumption of clock network and detect the activity of the cell efficiently, asynchronous architecture is full exploited. The proposed FPGA is fabricated in a 90 nm CMOS process with dual threshold voltages. It is more efficient in power than the synchronous FPGA at less than 30% utilization.
Keywords
CMOS digital integrated circuits; field programmable gate arrays; CMOS process; asynchronous architecture; autonomous fine-grain power-gating; clock network; low-power FPGA; size 90 nm; CMOS process; Clocks; Delay; Encoding; Energy consumption; Field programmable gate arrays; Sleep; Table lookup; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
978-1-4244-2748-2
Electronic_ISBN
978-1-4244-2749-9
Type
conf
DOI
10.1109/ASPDAC.2009.4796461
Filename
4796461
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