A dynamic quality-scalable H.264 video encoder chip

Author

Chang, Hsiu-Cheng ; Yang, Yao-Chang ; Chen, Jia-Wei ; Su, Ching-Lung ; Chien, Cheng-An ; Guo, Jiun-In ; Wang, Jinn-Shyan

Author_Institution

Nat. Chung-Cheng Univ., Chiayi

fYear

2009

fDate

19-22 Jan. 2009

Firstpage

125

Lastpage

126

Abstract

This paper proposes a dynamic quality-scalable H.264 video encoder that comprises 470 Kgates and 13.3 Kbytes SRAM using 1P8M 0.13 mum CMOS technology. Exploiting parameterized algorithms for motion estimation and intra prediction, the proposed design can dynamically configure the encoding modes with the design trade-off between power consumption and video quality for various video encoding applications. It achieves real-time H.264 video encoding on CIF, D1, and HD720@30 fps with 7 mW - 25 mW, 27 mW - 162 mW, and 122 mW - 183 mW power dissipation in different quality modes.

Keywords

CMOS integrated circuits; SRAM chips; motion estimation; video coding; CMOS technology; H.264 video encoder chip; SRAM; motion estimation; parameterized algorithms; video encoding; video quality; Algorithm design and analysis; CMOS technology; Clustering algorithms; Costs; Encoding; Energy consumption; Hardware; High definition video; Motion estimation; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

978-1-4244-2748-2

Electronic_ISBN

978-1-4244-2749-9

Type

conf

DOI

10.1109/ASPDAC.2009.4796464

Filename

4796464