Title :
A multi-task-oriented security processing architecture with powerful extensibility
Author :
Cao, Dan ; Han, Jun ; Zeng, Xiao-Yang ; Lu, Shi-ting
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It´s demonstrated that this architecture greatly improves the system efficiency. A test chip is implemented based on SMIC 0.18 um standard CMOS technology, and its functionality is well verified.
Keywords :
cryptography; microprocessor chips; SMIC; crypto-engines; microprocessor; multiple security processors; multitask-oriented security processing architecture; standard CMOS technology; CMOS technology; Communication system security; Cryptography; Data security; Data structures; Power system security; Scalability; Switches; System buses; Testing;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796468
