Partial order method for timed simulation of system-level MPSoC designs

Current discrete event simulator requires heavy simulation overhead to switch between different components to simulate them in strictly chronological order. Therefore, timed simulation is significantly slower than un-timed simulation. By simply adding delays in the components and communication channels, our timed MPEG-2 decoder simulates more than 14 times slower than an un-timed simulation. In this paper, we propose a partial order method to speed up timed simulation by relaxing the order that the components are simulated. With partial order method, a component is not required to schedule a channel access if both behavioral and timing results of the access are known. The simulation switches less frequently hence the simulation overhead reduces. We show that partial order method can be used in complex system-level simulation such as MPSoC implementations of the MPEG-2 decoder. In our experiments, partial order method provides more than 10 times speedups over regular discrete event simulation for timed simulation.