DocumentCode
2925187
Title
Towards a Java bytecodes compiler for Nios II soft-core processor
Author
Lima, Willian S. ; Lobato, Renata S. ; Manacero, Aleardo, Jr. ; Spolon, Roberta
Author_Institution
DCCE, UNESP - Sao Paulo State Univ., Sao Paulo, Brazil
fYear
2009
fDate
5-8 July 2009
Firstpage
104
Lastpage
109
Abstract
Reconfigurable computing is one of the most recent research topics in computer science. The Altera¿ Nios II soft-core processor can be included in a large set of reconfigurable architectures, especially because it is designed in software, allowing it to be configured according to the application. The recent growth in applications that demand reconfigurable computing made necessary the building of compilers that translate high level languages source codes into reconfigurable devices instruction sets. In this paper we present a compiler that takes as input the bytecodes generated by a Java front-end compiler and generates a set of instructions that attends to the Nios II processor instruction set rules. Our work shows how we process Java bytecodes to the intermediate code, in the Nios II instructions format, and build the control flow and the control dependence graphs.
Keywords
Java; data flow graphs; instruction sets; program compilers; program interpreters; Altera Nios II soft-core processor; JaNi; Java bytecode compiler; Java front-end compiler; bytecode generation; control dependence graph; control flow graph; high-level language source code translation; reconfigurable computing; reconfigurable device instruction set; Application software; Buildings; Computer aided instruction; Computer science; Hardware; High level languages; Java; Program processors; Reconfigurable architectures; Software design;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 2009. ISCC 2009. IEEE Symposium on
Conference_Location
Sousse
ISSN
1530-1346
Print_ISBN
978-1-4244-4672-8
Electronic_ISBN
1530-1346
Type
conf
DOI
10.1109/ISCC.2009.5202253
Filename
5202253
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