• DocumentCode
    2925320
  • Title

    Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration

  • Author

    Edahiro, Masato

  • Author_Institution
    Syst. IP Core Res. Labs., NEC Corp., Kawasaki
  • fYear
    2009
  • fDate
    19-22 Jan. 2009
  • Firstpage
    230
  • Lastpage
    233
  • Abstract
    Fundamental algorithms should be parallelized to accelerate EDA software on multi-core architecture. In this paper, we introduce scalable algorithms that have scalability on multi-cores. As an example, a sorting algorithm, called Map Sort, is presented. This algorithm uses a map from subsets of input data to intervals on data range. Experimental results show that, in comparison with quick sort on a single CPU, processing time of Map Sort is comparable on a CPU and three times faster on four CPUs.
  • Keywords
    electronic design automation; multiprocessing systems; parallel processing; EDA acceleration; Map Sort; electronic design automation; multicore processors; symmetric parallel processing; Acceleration; Central Processing Unit; Electronic design automation and methodology; Laboratories; Multicore processing; National electric code; Parallel processing; Scalability; Software algorithms; Sorting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    978-1-4244-2748-2
  • Electronic_ISBN
    978-1-4244-2749-9
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2009.4796485
  • Filename
    4796485