Logic design with evolving truth-table (LoDETT) for pattern recognition LSIs

Author

Yasunaga, Moritoshi ; Takahashi, Masatoshi

Author_Institution

Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan

fYear

1998

fDate

4-9 May 1998

Firstpage

318

Lastpage

323

Abstract

Presents a general and consistent design and fabrication process for pattern recognition LSI chips. In the process, the truth-table converted from the sample patterns is evolved to obtain generalization for unknown patterns, and the table is implemented on the reconfigurable LSI chips. With this process, named LoDETT (Logic Design with Evolving Truth-Table), the highly parallel hardware specialized for each task is easily fabricated with a quick turnaround time at each user site. We apply LoDETT to the English pronunciation recognition task and show the implementation results and performance

Keywords

genetic algorithms; integrated circuit manufacture; integrated logic circuits; large scale integration; logic CAD; parallel machines; pattern recognition equipment; special purpose computers; English pronunciation recognition task; IC design process; IC fabrication process; LoDETT; evolving truth table; generalization; implementation results; logic design; parallel hardware; pattern recognition LSI chips; performance; reconfigurable LSI chips; sample patterns; turnaround time; user sites; Databases; Fabrication; Field programmable gate arrays; Hardware; Large scale integration; Logic design; Pattern matching; Pattern recognition; Process design; Synthesizers;

fLanguage

English

Publisher

ieee

Conference_Titel

Evolutionary Computation Proceedings, 1998. IEEE World Congress on Computational Intelligence., The 1998 IEEE International Conference on

Conference_Location

Anchorage, AK

Print_ISBN

0-7803-4869-9

Type

conf

DOI

10.1109/ICEC.1998.699752

Filename

699752