Title :
A 3D prototyping chip based on a wafer-level stacking technology
Author :
Miyakawa, Nobuaki
Author_Institution :
Honda Res. Inst. Japan Co., Ltd., Wako
Abstract :
We have developed a new 3-dimensional stacking technology using wafer-to-wafer stacked method and evaluated the connectivity between TSV and micro-bump. The prototype 3-layer stacking device has been tried using our technology and the functional yield reached more than 60%. Using 8-inch wafer. We propose one of the design methodologies for a 3D stacked device.
Keywords :
integrated circuit packaging; prototypes; stacking; 3-dimensional stacking technology; 3D prototyping chip; TSV; microbump; size 8 inch; wafer-level stacking technology; wafer-to-wafer stacked method; Conducting materials; Contact resistance; Design methodology; Electric resistance; Fabrication; Large scale integration; Prototypes; Stacking; Through-silicon vias; Wet etching;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796516
