Configurable architecture for smart pixel research

Author

Raman, K. Shankar ; Chokhani, Arvind ; Vagheeswar, V. Sathya ; Beyette, Fred R., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng. & Comput. Sci., Cincinnati Univ., OH, USA

Volume

2

fYear

2002

fDate

10-14 Nov. 2002

Firstpage

905

Abstract

A new and efficient design of a 4 × 4 array of single bit optical reduced instruction set computer (RISC) processors demonstrating data distribution through an integrated CMOS photodetector and photoreceiver alleviating bandwidth and interconnect delay limitations is presented. The proposed chip monolithically integrates optical sensors with CMOS based logic circuits with a RISC to create a generically programmable smart pixel.

Keywords

CMOS logic circuits; integrated optoelectronics; optical computing; optical interconnections; optical receivers; photodetectors; reduced instruction set computing; smart pixels; 4 by 4 array; CMOS based logic circuits; bandwidth limitations; configurable architecture; design; generically programmable smart pixel; integrated CMOS photodetector; interconnect delay limitations; optical sensors; photoreceiver; single bit optical reduced instruction set computer processors; smart pixel research; Computer aided instruction; Computer architecture; Distributed computing; Integrated optics; Optical arrays; Optical design; Optical interconnections; Optical sensors; Reduced instruction set computing; Smart pixels;

fLanguage

English

Publisher

ieee

Conference_Titel

Lasers and Electro-Optics Society, 2002. LEOS 2002. The 15th Annual Meeting of the IEEE

ISSN

1092-8081

Print_ISBN

0-7803-7500-9

Type

conf

DOI

10.1109/LEOS.2002.1159602

Filename

1159602