Title :
Addressing thermal and power delivery bottlenecks in 3D circuits
Author :
Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN
Abstract :
The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
Keywords :
integrated circuit design; integrated circuit packaging; power integrated circuits; 3D integrated circuit technology; packing densities; power delivery bottlenecks; thermal delivery; Equations; Finite difference methods; Packaging; Power generation; Power grids; Steady-state; Temperature; Thermal conductivity; Thermal management; Three-dimensional integrated circuits;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796518
