Power analysis of 3T DRAM cell using FinFET at 45nm process technology

The intention of this paper is to reduce leakage power and leakage current of 3T DRAM while maintaining the competitive performance. A new high performance 3T DRAM using FINFET on new logic approach is presented in this paper. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. FinFETs are double-gate devices. The two gates of a FinFET can either be shorted for higher recital or independently restricted for lower leakage or reduced transistor count. Many advanced processors now have on chip instructions and data memory using DRAMs. The major contribution of power dissipation in DRAM cell is off-state leakage current. Thus, improving the power efficiency of a DRAM cell is critical to the overall system power dissipation. We investigate the use FinFET CMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt transistors for logic cells and low leakage, high Vt of transistor and show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 6ns access time and frequency 0.16 GHz provide 45nm CMOS process technology with 0.7V power supply is employed to carry out 3T DRAM cell using FinFET.