DocumentCode :
2926479
Title :
On using SAT to ordered escape problems
Author :
Luo, Lijuan ; Wong, Martin D F
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL
fYear :
2009
fDate :
19-22 Jan. 2009
Firstpage :
594
Lastpage :
599
Abstract :
Routing for high-speed boards is largely a time-consuming manual task today. The ordered escape routing problem is one of the key problems in board-level routing, and Boolean satisfiability (SAT) based approach [1] is the only solution to this problem so far. In this paper, we first solve the major deficiency of the original SAT formulation so that the escape problem is completely resolved. Then we propose two techniques to extend SAT approach for large-scale problems. Experimental results on industrial benchmarks show that our methods perform well in terms of both speed and routability.
Keywords :
circuit CAD; computability; high-speed integrated circuits; integrated circuit design; network routing; Boolean satisfiability; SAT; board-level routing; high-speed boards; ordered escape routing; Clocks; Integer linear programming; Large-scale systems; Pins; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
Type :
conf
DOI :
10.1109/ASPDAC.2009.4796545
Filename :
4796545
Link To Document :
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