Title :
Dependent latch identification in the reachable state space
Author :
Lin, Chen-Hsuan ; Wang, Chun-Yao
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu
Abstract :
The large number of latches in current designs increase the complexity of formal verification and logic synthesis, since the growth of latch number leads the state space to explode exponentially. One solution to this problem is to find the functional dependencies among these latches. Then, these latches can be identified as dependent latches or essential latches, where the state space can be constructed using only the essential latches. This paper proposes an approach to find the functional dependencies among latches in a sequential circuit by using SAT solvers with the Craig interpolation theorem. In addition, the proposed approach detects sequential functional dependencies existing in the reachable state space only. Experimental results show that our approach could deal with large sequential circuits with up to 1.5 K latches in a reasonable time and simultaneously identify the combinational and sequential dependent latches.
Keywords :
flip-flops; formal verification; interpolation; logic design; sequential circuits; Craig interpolation theorem; SAT solvers; dependent latch identification; formal verification; functional dependency; logic design; logic synthesis; reachable state space; sequential circuits; Binary decision diagrams; Boolean functions; Circuit testing; Data structures; Formal verification; Interpolation; Latches; Reachability analysis; Sequential circuits; State-space methods;
Conference_Titel :
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
978-1-4244-2748-2
Electronic_ISBN :
978-1-4244-2749-9
DOI :
10.1109/ASPDAC.2009.4796551