Fault modeling and testing of retention flip-flops in low power designs

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologies are not sufficient to test the retention flip-flop thoroughly. This paper presents four new fault models and the testing of retention flip-flop. The four fault models are awake-mode stuck-at fault, sleep-mode stuck-at fault, awake-mode transition fault, and sleep-mode transition fault. The four faults model the defects that affect the retained value, wakeup time, and sleep time of retention flip-flops. Based on the new fault models, test patterns for retention flip-flop can be easily generated by current automatic test pattern generation tools. The proposed test methodology is validated by performing experiments on ISCAS´89 benchmark circuits and some realistic industrial low power designs. The experimental results show that the faults of retention flip-flops can be easily detected by our method and the average fault coverage is higher than 98%. The fault coverage of conventional single stuck-at fault and transition fault test can be increased by more than 1%.