Title :
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering
Author :
Tze-Yun Sung ; Yaw-Shih Shieh ; Yu, Chun-wang ; Hsi-Chin Hsin
Author_Institution :
Dept. of Microelectron. Eng., Chung Hua Univ., Hsinchu
Abstract :
High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3D rotation for high throughput 3D vector interpolation are presented in this paper. The primitives are based on the CORDIC algorithm. The proposed architecture of the 3D vector interpolator using redundant CORDIC arithmetic is presented in this paper. The high-throughput 3D vector interpolator is implemented by VLSI
Keywords :
VLSI; digital arithmetic; interpolation; power aware computing; rendering (computer graphics); 3D vector interpolation; VLSI; power-aware 3D graphics rendering; redundant CORDIC arithmetic; Algorithm design and analysis; Arithmetic; Delay; Graphics; Hardware; Interpolation; Pipeline processing; Rendering (computer graphics); Throughput; Very large scale integration; 3-D vector interpolation; CORDIC algorithm; Redundant CORDIC arithmetic; high-throughput.;
Conference_Titel :
Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7695-2736-1
DOI :
10.1109/PDCAT.2006.7
