• DocumentCode
    2927222
  • Title

    Modeling two way concurrent buffer system using timed automata in UPPAAL

  • Author

    Mishra, Ravishankar ; Zeeshaan, M. ; Singh, Sushil

  • Author_Institution
    Dept. of Inf. & Commun. Technol., Manipal Inst. of Technol., Manipal, India
  • fYear
    2012
  • fDate
    Oct. 30 2012-Nov. 2 2012
  • Firstpage
    846
  • Lastpage
    851
  • Abstract
    Two way buffer system is a system that exhibits transfer of data using two buffers concurrently. It includes processes that synchronize to exchange data with each other along with executing certain delays between these synchronizations. In existing Tiny two way buffer system, both generators produce packets in half duplex manner after a delay of 10 seconds. However, generator one has an initial shift of 5 seconds after which it begins sending a packet every 10 seconds. Hence, initial delay for generator one is 15 seconds and for generator two it is 10 seconds. Due to this initial shift, both generators produce packets alternatively and is deadlock free as the packets do not meet at the same time instant. Moreover, the existing system model is not concurrent and hence takes more time for packet transfer in every iteration. In this paper we have proposed a model of buffer system using an additional dummy buffer for transfer of data packets, by introducing delay in various buffers of the proposed system that speeds up the transfer of packets. As a result the transfer of data becomes concurrent, deadlock free and hence the model proposed is time efficient. To model and simulate the proposed system we have used UPPAAL as a model checking tool environment for modeling, validation and verification of real-time systems modeled as networks of timed automata. Simulation results shows that the proposed two way buffer system is fully concurrent and time efficient as compared to the existing buffer system.
  • Keywords
    concurrency control; finite state machines; formal verification; real-time systems; UPPAAL; concurrent buffer system; data exchange; data packet transfer; dummy buffer; model checking tool environment; real-time system modeling; real-time system validation; real-time system verification; synchronizations; timed automata; Automata; Delay; Generators; Model checking; Synchronization; System recovery; Concurrent Buffer System; Model Checking; Real Time Systems; Timed Automata; UPPAAL;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information and Communication Technologies (WICT), 2012 World Congress on
  • Conference_Location
    Trivandrum
  • Print_ISBN
    978-1-4673-4806-5
  • Type

    conf

  • DOI
    10.1109/WICT.2012.6409193
  • Filename
    6409193