A new sub-300mV 8T SRAM cell design in 90nm CMOS

In this paper, we present a new 8 transistors (8T) design for Static Random Access Memory (SRAM) cell. In this design during write operation one of the inverters of the cell becomes weaker so that changing the stored data in the cell is more likely in write operation. This leads to increase the write ability of the cell. We used one PMOS and one NMOS transistor to float supply voltage and ground rails and therefore making the cell weaker. By separating the write and read access transistors, we could size them individually so the read Static Noise Margin (SNM) and read stability can be increased. Our design satisfies 4.5σ criterion for writing and reading at supply voltage of 300mV and 3.7σ at 250mV. Simulation results in 90nm technology show that the proposed 8T SRAM cell decreases write and read delays by 45% and 58% over conventional 6T SRAM cell at supply voltage of 500mV, where the power consumption for single write operation is decreased by 54%. Finally, the proposed 8T SRAM cell has been redesigned using 16nm PTM Bulk and FinFET transistors. The simulation results show considerable improvement of hold and read SNMs for FinFET.