High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Author

Sung, Tze-Yun ; Shieh, Yaw-Shih ; Yu, Chun-Wang ; Hsin, Hsi-Chin

Author_Institution

Dept. of Microelectron. Eng., Chung Hua Univ., Hsinchu

fYear

2006

fDate

Dec. 2006

Firstpage

191

Lastpage

196

Abstract

Two dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8times8 DCT and IDCT processors. In which, two 8-point DCT/IDCT processors with dual-bank of SRAM (128 words) and coefficient ROM (6 words), two multiplexers, and control unit are involved. The kernel arithmetic unit (AU) is designed by using CORDIC arithmetic. The proposed architectures for 2D DCT/IDCT processors not only simplify hardware but also reduce the power consumption with high performances

Keywords

digital arithmetic; digital signal processing chips; discrete cosine transforms; parallel architectures; 2D discrete cosine transform; CORDIC rotation; ROM; SRAM; inverse discrete cosine transform; kernel arithmetic unit; parallel structure; pipelined structure; Arithmetic; Discrete cosine transforms; Energy consumption; Gold; Hardware; Image processing; Kernel; Multiplexing; Random access memory; Read only memory; CORDIC; DCT; IDCT; low-power;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on

Conference_Location

Taipei

Print_ISBN

0-7695-2736-1

Type

conf

DOI

10.1109/PDCAT.2006.70

Filename

4032176