DocumentCode
2927549
Title
Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy
Author
Sun, Caixia ; Tang, Hongwei ; Zhang, Minxuan
Author_Institution
Coll. of Comput., Nat. Univ. of Defense Technol., Changsha
fYear
2006
fDate
Dec. 2006
Firstpage
217
Lastpage
222
Abstract
In simultaneous multithreading (SMT) processors, the instruction fetch policy affects the speed at which each thread runs and overall throughput. However, current fetch policies almost focus on overall throughput optimization, and provide no control over how fast individual threads run. As a result, the performance of a thread varies with fetch policy and the workload it is executed. This performance unpredictability means that the execution time of a thread is unpredictable. So only depending on the operating system (OS) thread scheduler to guarantee the execution time constraint of a time critical thread is not enough even fails. The hardware must ensure that the performance of the time critical thread is predictable in any timeslice. In this paper, we propose a novel fetch policy to control performance of a time critical thread in SMT processors. We evaluate our policy using many different workloads, and results show that for more than 94% of all cases measured, our policy can achieve the desired performance. For the failing cases, the average variance is within 1.25%. Furthermore, our policy does not sacrifice overall throughput severely. Compared to fetch policies orienting towards throughput maximization such as ICOUNT, the average degradation of overall throughput is less than 3%. Especially, our policy makes efforts to maximize the throughput of all coscheduled threads other than the time critical one, and gives 98.25% of the throughput achieved by ICOUNT on average
Keywords
instruction sets; microprocessor chips; multi-threading; surface mount technology; ICOUNT; SMT processors; instruction fetch policy; operating system thread scheduler; performance unpredictability; simultaneous multithreading processors; throughput optimization; time-critical thread; Computer aided instruction; Educational institutions; Multithreading; Processor scheduling; Real time systems; Resource management; Surface-mount technology; Throughput; Time factors; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on
Conference_Location
Taipei
Print_ISBN
0-7695-2736-1
Type
conf
DOI
10.1109/PDCAT.2006.48
Filename
4032181
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