AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation

Author

Moh, Abidalrahman ; Jararweh, Yaser ; Tawalbeh, Lo´ai

Author_Institution

Eng. Math. & Internetworking, Dalhousie Univ., Halifax, NS, Canada

fYear

2011

fDate

5-8 Dec. 2011

Firstpage

292

Lastpage

297

Abstract

This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.

Keywords

cryptography; field programmable gate arrays; hardware description languages; AES algorithm; AES-512; FPGA architecture; VHDL; Virtex-7 chips; Virtix-6 chips; advanced encryption standard; cryptanalysis; Algorithm design and analysis; Encryption; Field programmable gate arrays; Hardware; Polynomials; Throughput; Advanced Encryption Standard; Cryptography; Enhanced Security; FPGA;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Assurance and Security (IAS), 2011 7th International Conference on

Conference_Location

Melaka

Print_ISBN

978-1-4577-2154-0

Type

conf

DOI

10.1109/ISIAS.2011.6122835

Filename

6122835