A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology

Author

Ming-Shuan Chen ; Yang, Chih-Kong Ken

Author_Institution

UCLA, Los Angeles, CA, USA

Volume

50

Issue

8

fYear

2015

fDate

Aug. 2015

Firstpage

1903

Lastpage

1916

Abstract

This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.

Keywords

CMOS digital integrated circuits; delay lines; equalisers; feedforward; CMOS technology; LC ladder filter based FFE; bit rate 50 Gbit/s to 64 Gbit/s; delay line; feedforward equalizer; multiplexing circuit; output combiner; serializing transmitter; size 65 nm; Bandwidth; Capacitance; Clocks; Delay lines; Delays; Inductors; Transmitters; High speed; LC-ladder filter; feedforward equalizer (FFE); multiplexer; serial link; serializer; transmitter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2015.2411625

Filename

7086344