Title : 
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications
         
        
            Author : 
Liang, Zheng ; Plosila, Juha ; Yan, Lu ; Sere, Kaisa
         
        
            Author_Institution : 
Turku Centre for Comput. Sci.
         
        
        
        
        
        
            Abstract : 
This paper presents an advanced self-timed Java accelerator core which has extremely low power consumption while providing sufficient performance for even the most demanding real-time telecommunication and multimedia applications. The goal is that the accelerator can be directly attached to any general-purpose processor core running some Java-intensive application software. Asynchronous self-timed circuit technology, where timing is based on local handshakes between circuit blocks instead of a global clock signal, provides a promising platform for obtaining a highly modular low-power Java accelerator implementation
         
        
            Keywords : 
Java; low-power electronics; network-on-chip; power aware computing; real-time systems; timing circuits; Java-intensive application software; asynchronous self-timed circuit technology; circuit block; general-purpose processor core; global clock signal; local handshake; low power consumption; multimedia application; network-on-chip application; real-time telecommunication; self-timed Java accelerator; timing; Application software; Circuits; Clocks; Computer languages; Computer science; Energy consumption; Java; Network-on-a-chip; Timing; Virtual machining;
         
        
        
        
            Conference_Titel : 
Parallel and Distributed Computing, Applications and Technologies, 2006. PDCAT '06. Seventh International Conference on
         
        
            Conference_Location : 
Taipei
         
        
            Print_ISBN : 
0-7695-2736-1
         
        
        
            DOI : 
10.1109/PDCAT.2006.72