DocumentCode :
292813
Title :
Time-zone: a new algorithm for register allocation in data path synthesis
Author :
Jong, Ching Chuen ; Lam, Yvonne Y. H. ; Lim, S.S.
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ.
Volume :
1
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
37
Abstract :
A new algorithm named the time-zone algorithm for solving register allocation problem in the automatic data path synthesis is presented in this paper. The time-zone algorithm was developed from the left-edge algorithm with which the number of registers can be minimized. The time-zone algorithm was developed to minimize the number of registers as well as the interconnections and the number of multiplexers required for the registers. The experimental results obtained from testing several published examples show that the interconnections are improved and the number of multiplexers is reduced while at the same time the number of registers is still minimized
Keywords :
circuit layout CAD; high level synthesis; integrated circuit layout; data path synthesis; interconnections minimisation; left-edge algorithm; multiplexers reduction; register allocation; time-zone algorithm; Data engineering; Hardware; High level synthesis; Microelectronics; Multiplexing; Performance evaluation; Scheduling algorithm; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.408749
Filename :
408749
Link To Document :
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