DocumentCode
292818
Title
A unified algorithm for estimation and scheduling in data path synthesis
Author
Hu, Yuan ; Carlson, Bradley S.
Author_Institution
Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
57
Abstract
A unified algorithm is presented to solve the problem of estimation and scheduling for performance constrained data path synthesis. The algorithm achieves superior results by first computing a lower bound on the number of functional units required to satisfy the performance constraint T, and then scheduling the operations into the best control steps using the lower bound algorithm. The lower bound not only greatly reduces the size of the solution space, but also provides a means to measure the proximity of the final solution to an optimal one. Our unified algorithm can also be incorporated in a branch-and-bound algorithm to solve the scheduling problem optimally. Experiments indicate that our scheduling algorithm can produce results very close to the lower bound. For all of the test cases the difference between our upper and lower bounds is not greater than one
Keywords
circuit CAD; estimation theory; integrated circuit design; logic CAD; scheduling; branch/bound algorithm; data path synthesis; estimation; performance constrained synthesis; scheduling; unified algorithm; Algorithm design and analysis; Computational modeling; Flow graphs; Integrated circuit modeling; Integrated circuit synthesis; Processor scheduling; Scheduling algorithm; State estimation; Testing; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408754
Filename
408754
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