DocumentCode
292819
Title
High level synthesis with testability constraints
Author
BenHamida, Naim ; Kaminska, Bozena
Author_Institution
Dept. of Electr. Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
65
Abstract
In this paper, a new approach to high-level synthesis testability evaluation is introduced. This approach consists of two phases: abstraction and propagation. In the abstraction phase, the function´s primitive testability measures are abstracted from their oBDD representation. Then, the testability measure is propagated to evaluate data path testability and used in the synthesis for testability process. The choice of a testable design and the modification of a data flow during or after the scheduling and allocation phases are shown to be efficient
Keywords
Boolean functions; design for testability; high level synthesis; logic testing; abstraction phase; allocation phase; data flow; data path testability; high level synthesis; oBDD representation; primitive testability measures; propagation phase; scheduling; testability constraints; testable design; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; High level synthesis; Integrated circuit interconnections; Observability; Phase estimation; Phase measurement; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408756
Filename
408756
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