Title :
A method of representative fault selection in digital circuits for ATPG
Author :
Sang-in, Akachai ; Cheung, Peter Y K
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
fDate :
30 May-2 Jun 1994
Abstract :
A new method of representative fault selection in digital circuits based on the concepts of test equivalent and test implied faults is introduced in order to minimise the number of target faults to be considered in ATPG and fault simulation. Experimental results on a set of ISCAS benchmark combinational and sequential circuits have shown a significant reduction in the number of target faults when compared with other recently published techniques
Keywords :
Boolean functions; automatic testing; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; sequential circuits; ATPG; ISCAS benchmark circuits; combinational circuits; digital circuits; fault simulation; representative fault selection; sequential circuits; target faults; test equivalent faults; test implied faults; Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Digital circuits; Electronic equipment testing; Logic circuits; Medical tests; Test pattern generators;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.408758
